1. Field of the Invention
The present invention relates to a semiconductor device in which moisture resistance in a multilayered wire structure is improved and a method of manufacturing the same, and a phase shift mask usable in manufacturing the semiconductor device.
2. Description of the Related Art
In recent years, a design rule of the multilayered wire structure has a tendency to be reduced in size as the LSI makes its transition. For this reason, some of wires, which are formed by forming a film for metal wire material and directly etching the film, are too small to manufacture. Hence, the following method is adopted as the method of forming the wire. That is, after forming an interlayer insulation film, a trench pattern or a hole pattern is formed in this interlayer insulation film, and a wire material is embedded in an opening region of the pattern, thereby forming the wire. This method of forming the wire is referred to as a damascene method.
When the wire is formed by the etching, W, Al or an Al alloy is often used as a wire material. However, when the damascene method is employed, Cu is sometimes used because of its low electric resistance and high resistance to electromigration.
In manufacturing the semiconductor device, elements such as transistors, contacts, wires, pads are formed on a semiconductor wafer. Thereafter, the semiconductor wafer is divided into a plurality of chips, each of which is packaged using ceramic or plastic.
In order to speed up a transmission rate of a signal, which is important for performance of the wire, reduction in capacitance between wires and in capacitance parasitic between wires which are provided in different layers is effective. Therefore, emphasis has been recently placed on lowering a dielectric constant of an insulation film which exists between the wires provided in the same layer and of the interlayer insulation film which exists between the wires provided in the different layers, as well as lowering the resistance of the wire itself. Further, in order to lower the dielectric constant, a fluorine-doped silicon oxide film, an inorganic insulation film, an organic insulation film, and the like other than a silicon oxide film are recently used as the interlayer insulation film, instead of the silicon oxide film. In general, as a distance between atoms or molecules of the material becomes larger, the dielectric constant becomes lower due to simple lowering of a film density.
However, a coefficient of thermal expansion of the above-described interlayer insulation film having the low dielectric constant is substantially different from coefficients of thermal expansion of other constituting materials such as a substrate. Because of this difference in the coefficient of thermal expansion, large thermal stress is generated by the heat treatment to follow. The thermal stress is concentrated on a corner of the chip to cause stress concentration, and peeling between layers or a crack may occur at the corner of the chip. When the crack is caused, moisture as a disturbance easily enters into the chip. The stress concentration due to the difference in the coefficient of thermal expansion like the above is especially significant in the semiconductor device to which the damascene method is adopted. The reason is that, according to the damascene method, an abundance of portions whose coefficients of thermal expansion are substantially different from each other exist, because the interlayer insulation film is formed on a flattened wire layer or the like, the trench pattern or the like is formed in the interlayer insulation film, and thereafter, the wire material is embedded in the opening region. Therefore, the conventional semiconductor device to which the damascene method is adopted has a disadvantage that it is difficult to secure a sufficient moisture resistance.